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tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 1 post office box 655303 ? dallas, texas 75265 four 8-bit d/a converters with individual references direct bipolar operation without an external level-shift amplifier microprocessor compatible ttl/cmos compatible single supply operation possible simultaneous update facility binary input coding applications process control automatic test equipment automatic calibration of large system parameters e.g., gain/offset description the tlc7225 consists of four 8-bit voltage-output digital-to-analog converters (dacs), with output buffer amplifiers and interface logic with double register-buffering. separate on-chip latches are provided for each of the dacs. data is transferred into one of these data latches through a common 8-bit ttl/cmos-compatible (5 v) input port. control inputs a0 and a1 determine which dac is loaded when wr goes low. only the data held in the dac registers determines the analog outputs of the converters. the double register buffering allows simultaneous update of all four outputs under control of ldac . all logic inputs are ttl- and cmos-level compatible and the control logic is speed compatible with most 8-bit microprocessors. each dac includes an output buffer amplifier capable of driving up to 5 ma of output current. the tlc7225 performance is specified for input reference voltages from 2 v to v dd ? 4 v with dual supplies. the voltage-mode configuration of the dacs allow the tlc7225 to be operated from a single power-supply rail at a reference of 10 v. the tlc7225 is fabricated in a linbicmos ? process that has been specifically developed to allow high-speed digital logic circuits and precision analog circuits to be integrated on the same chip. the tlc7225 has a common 8-bit data bus with individual dac latches. this provides a versatile control architecture for simple interface to microprocessors. all latch-enable signals are level triggered. combining four dacs, four operational amplifiers, and interface logic into a small, 0.3-inch wide, 24-terminal soic allows significant reduction in board space requirements and offers increased reliability in systems using multiple converters. the pinout optimizes board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at the other. the tlc7225c is characterized for operation from 0 c to 70 c. the tlc7225i is characterized for operation from ? 25 c to 85 c. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 outb outa v ss refb refa agnd dgnd ldac (msb) db7 db6 db5 db4 outc outd v dd refc refd a0 a1 wr db0 (lsb) db1 db2 db3 dw package (top view) production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2001, texas instruments incorporated linbicmos is a trademark of texas instruments.
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 2 post office box 655303 ? dallas, texas 75265 available options packaged devices t a small outline (dw) 0 c to 70 c TLC7225CDW ? 25 c to 85 c tlc7225idw functional block diagram _ + dac a input latch a 8 _ + 8 _ + 8 _ + 8 control logic 8 refa db0 ? db7 wr a0 a1 outa outb outc outd refb refc refd input latch b input latch c input latch d dac b dac c dac d dac latch a dac latch b dac latch c dac latch d ldac 5 4 9?16 21 20 8 17 19 18 2 1 24 23 schematic of outputs output 450 a v dd v ss equivalent analog output 100 a
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description agnd 6 analog ground a0, a1 18, 19 i dac select inputs dgnd 7 digital ground db0 ? db7 9 ? 16 i digital dac data inputs ldac 8 load dac. a high level simultaneously loads all four dac registers. dac registers are transparent when ldac is low. outa 2 o daca output outb 1 o dacb output outc 24 o dacc output outd 23 o dacd output refa 5 i voltage reference input to daca refb 4 i voltage reference input to dacb refc 21 i voltage reference input to dacc refd 20 i voltage reference input to dacd v dd 22 positive supply voltage v ss 3 negative supply voltage wr 17 i write input selects dac transparency or latch mode absolute maximum ratings over operating free-air temperature range (unless otherwise note) ? supply voltage range, v dd : to agnd or dgnd ? 0.3 v to 17 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to v ss ? 0.3 v to 24 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v ss : to agnd or dgnd ? 7 v to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range between agnd and dgnd ? 0.3 v to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (to dgnd) ? 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference voltage range, v ref (to agnd) ? 0.3 v to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (to agnd) (see note 1) v ss to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation at (or below) t a = 25 c (see note 2) 500 mw . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range: c suffix 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i suffix ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. output voltages may be shorted to agnd provided that the power dissipation of the package is not exceeded. typically sh ort circuit current to agnd is 50 ma. 2. for operation above t a = 75 c derate linearly at the rate of 2.0 mw/ c.
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions min max unit supply voltage, v dd 11.4 16.5 v supply voltage, v ss ? 5.5 0 v high-level input voltage, v ih 2 v low-level input voltage, v il 0.8 v reference voltage, v ref 2 v dd ? 4 v load resistance, r l 2 k ? o p erating free air tem p erature t a c suffix 0 70 c operating free - air temperature , t a i suffix ? 25 85 c timing requirements (see figure 1) parameter test conditions min max unit t su(aw) setup time, address valid before wr 0 ns t su(dw) setup time, data valid before wr v dd = 11.4 v to 16.5 v, v ss = 0 or ? 5 v 45 ns t h(aw) hold time, address valid after wr v dd = 11.4 v to 16.5 v, v ss = 0 or ? 5 v 0 ns t h(dw) hold time, data valid after wr v dd = 11.4 v to 16.5 v, v ss = 0 or ? 5 v 10 ns t w1 pulse duration, wr low v dd = 11.4 v to 16.5 v, v ss = 0 or ? 5 v 50 ns t w2 pulse duration, ldac low v dd = 11.4 v to 16.5 v, v ss = 0 or ? 5 v 50 ns
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range reference inputs (all supply ranges) parameter test conditions min typ max unit r i input resistance, refa, refb, refc, refd 1.5 4 k ? c i in p ut ca p acitance refa refb refc refd dac loaded with all 1s 300 pf c i in ut ca acitance , refa , refb , refc , refd dac loaded with all 0s 65 pf channel-to-channel isolation v f = 10 v sine wave at 10 khz 60 db ac feedthrough v ref = 10 v pp sine wave at 10 khz 70 db dual power supply over recommended supply and reference voltage ranges, agnd = dgnd = 0 v (unless otherwise noted) parameter test conditions min typ max unit i i input current, digital v i = 0 or v dd 1 a i dd supply current, v dd v i = v il or v ih , no load 10 16 ma i ss supply current, v ss v i = v il or v ih , no load 4 10 ma power supply sensitivity ? v dd = 5% 0.01 %/% c i input capacitance digital inputs 8 pf single power supply, v dd = 14.25 v to 15.75 v, v ss = agnd = dgnd = 0 v, v ref (a, b, c, d) = 10 v parameter test conditions min typ max unit i i input current, digital v i = 0 or v dd 1 a i dd supply current, v dd v i = v il or v ih , no load 5 13 ma power supply sensitivity ? v dd = 5% 0.01 %/% c i input capacitance digital inputs 8 pf
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 6 post office box 655303 ? dallas, texas 75265 operating characteristics over recommended operating free-air temperature range dual power supply over recommended supply and reference voltage ranges, agnd = dgnd = 0 v (unless otherwise noted) parameter test conditions min typ max unit slew rate 2.5 v/ s t settling time to 1/2 lsb positive full scale v f(abcd) =10v 5 s t s settling time to 1/2 lsb negative full scale v ref(a, b, c, d) = 10 v 7 s resolution 8 bits total unadjusted error v dd = 15 v 5%, v ref(a, b, c, d) = 10 v 2 lsb integral nonlinearity (inl) v dd = 15 v 5%, v ref(a, b, c, d) = 10 v 1 lsb differential nonlinearity (dnl) v dd = 15 v 5%, v ref(a, b, c, d) = 10 v 1 lsb e fs full-scale error v dd = 15 v 5%, v ref(a, b, c, d) = 10 v 2 lsb e g gain error v dd = 15 v 5%, v ref(a, b, c, d) = 10 v 0.25 lsb temperature coefficient full-scale error v dd =14vto165v v f(abcd) =10v 20 ppm/ c of gain zero-code error v dd = 14 v to 16 . 5 v , v ref(a, b, c, d) = 10 v 50 v/ c zero-code error 20 80 mv digital crosstalk or feedthrough glitch impulse area v ref(a, b, c, d) = 0 50 nv ? s single power supply, v dd = 14.25 v to 15.75 v, v ss = agnd = dgnd = 0 v, v ref(a, b, c, d) = 10 v (unless otherwise noted) parameter test conditions min typ max unit slew rate 2 v/ s t settling time to 1/2 lsb positive full scale 5 s t s settling time to 1/2 lsb negative full scale 20 s resolution 8 bits total unadjusted error 2 lsb e fs full-scale error 2 lsb temperature coefficient of g ain full-scale error v dd = 14 v to 16.5 v, v ref(a, b, c, d) = 10 v 20 ppm/ c g zero-code error 50 v/ c differential nonlinearity error (dnl) 1 lsb digital crosstalk or feedthrough glitch impulse area 50 nv ? s
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 7 post office box 655303 ? dallas, texas 75265 parameter measurement information v dd 0 v v dd 0 v v dd 0 v data in address wr t h(aw) t w1 t su(aw) v dd 0 v data valid ldac t w2 t su(dw) t h(dw) notes: a. t r = t f = 20 ns over v dd range. b. the timing-measurement reference level is equal to v ih + v il divided by 2. c. if ldac is activated prior to the rising edge of wr , then it must remain low for at least t w2 after wr goes high. figure 1. write-cycle voltage waveforms typical characteristics figure 2 ? output current ? ma output current vs output voltage 200 150 100 50 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 2 ? 10 1 2 v o ? output voltage ? v i o source current short-circuit limiting sinking current source t a = 25 c v ss = ? 5 v db0 ? db7 = 0 v v dd = 15 v 200 100 600 0 012345 6 400 300 500 output current (sink) vs output voltage 700 78910 t a = 25 c v dd = 15 v v ss = ? 5 v v ss = 0 i o a v o ? output voltage ? v ? output current (sink) ? figure 3
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 8 post office box 655303 ? dallas, texas 75265 application information specification ranges for the tlc7225 to operate to rated specifications, the input reference voltage must be at least 4 v below the power supply voltage at the v dd terminal. this voltage differential is the overhead voltage required by the output amplifiers. the tlc7225 is specified to operate over a v dd range from 12 v 5% to 15 v 10% (i.e., from 11.4 v to 16.5 v) with a v ss of ? 5 v 10%. operation is also specified for a single supply with a v dd of 15 v 5%. applying a v ss of ? 5 v results in improved zero-code error, improved output sink capability with outputs near agnd, and improved negative-going settling time. performance is specified over the range of reference voltages from 2 v to (v dd ? 4 v) with dual supplies. this allows a range of standard refence generators to be used such as the tl1431, with an adjustable 2.5-v bandgap reference. note that an output voltage range of 0 v to 10 v requires a nominal 15 v 5% power supply voltage. dac section the tlc7225 contains four, identical, 8-bit voltage-mode dacs. each converter has a separate reference input. the output voltages from the converters have the same polarity as the reference voltages, thus allowing single supply operation. the simplified circuit diagram for channel a is shown in figure 4. note that agnd (terminal 6) is common to all four dacs. 2r 2r r r r _ + outa refa agnd 2r 2r 2r db0 db5 db6 db7 shown for all 1s on dac figure 4. dac simplified-circuit diagram the input impedance at any of the reference inputs is code dependent and can vary from 1.4 k ? minimum to an open circuit. the lowest input impedance at any reference input occurs when that dac is loaded with the digital code 01010101. therefore, it is important that the reference source presents a low output impedance under changing load conditions. the nodal capacitance at the reference terminals is also code dependent and typically varies from 60 pf to 300 pf. each outx terminal can be considered as a digitally programmable voltage source with an output voltage of: v outx = d x v refx where d x is the fractional representation of the digital input code and can vary from 0 to 255/256. the output impedance is that of the output buffer amplifier.
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 9 post office box 655303 ? dallas, texas 75265 application information output buffer each voltage-mode dac output is buffered by a unity-gain noninverting amplifier. this buffer amplifier is capable of developing 10 v across a 2-k ? load and can drive capacitive loads of 3300 pf. the tlc7225 can be operated as a single or dual supply; operating with dual supplies results in enhanced performance in some parameters which cannot be achieved with a single-supply operation. in a single supply operating (v ss = 0 v = agnd) the sink capability of the amplifier, which is normally 400 a, is reduced as the output voltage nears agnd. the full sink capability of 400 a is maintained over the full output voltage range by tying v ss to ? 5 v. this is indicated in figure 3. settling time for negative-going output signals approaching agnd is similarly affected by v ss . negative-going settling time for single supply operation is longer than for dual supply operation. positive-going settling-time is not affected by v ss . additionally, the negative v ss gives more headroom to the output amplifiers which results in better zero code performance and improved slew rate at the output than can be obtained in the single-supply mode. digital inputs the tlc7225 digital inputs are compatible with either ttl or 5-v cmos levels. to minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (v dd and dgnd) as practically possible. interface logic information the tlc7225 contains two registers per dac, an input register and a dac register. address lines a0 and a1 select which input register accepts data from the input port. when the wr signal is low, the input latches of the selected dac are transparent. the data is latched into the addressed input register on the rising edge of wr . table 1 shows the addressing for the input registers on the tlc7225. table 1. tlc7225 addressing control inputs selected input register a1 a0 register l l dac a input register l h dac b input register h l dac c input register h h dac d input register only the data held in the dac register determines the analog output of the converter. the ldac signal is common to all four dacs and controls the transfer of information from the input registers to the dac registers. data is latched into all four dac registers simultaneously on the rising edge of ldac . the ldac signal is level triggered and, therefore, the dac registers may be made transparent by tying ldac low (the outputs of the converters responds to the data held in their respective input latches). ldac is an asynchronous signal and is independent of wr . this is useful in many applications. however, in systems where the asynchronous ldac can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. in other words, if ldac is activated prior to the rising edge of wr (or wr occurs during ldac ), then ldac must stay low for a time of t w2 or longer after wr goes high to ensure that the correct data is latched through to the output. table 2 shows the truth table for tlc7225 operation. figure 5 shows the input control logic for the device and the write cycles timing diagram is shown in figure 1.
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 10 post office box 655303 ? dallas, texas 75265 application information table 2. tlc7225 truth table control inputs function wr ldac function h h no operation. device not selected l h input register of selected dac is transparent. h input register of selected dac is latched. h l all four dac registers are transparent (i.e., outputs respond to data held in respective input registers) input registers are latched. h all four dac registers are latched. l l dac registers and selected input register are transparent. output follows input data for selected channel. 19 18 17 a0 a1 wr to latch a to latch b to latch c to latch d figure 5. input control logic
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 11 post office box 655303 ? dallas, texas 75265 application information ground management and layout the tlc7225 contains four reference inputs that can be driven from ac sources (see multiplying dac using ac input to the ref terminals section) so careful layout and grounding is important to minimize analog crosstalk between the four channels. the dynamic performance of the four dacs depends upon the optimum choice of board layout. figure 6 shows the relationship between input frequency and channel-to-channel isolation. figure 7 shows a printed circuit board layout that minimizes crosstalk and feedthrough. the four input signals are screened by agnd. v ref was limited between 2 v and 3.24 v to avoid slew-rate limiting effects from the output amplifier during measurements. ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 20 k 50 k 100 k 200 k 500 k 1 m f i ? input frequency ? hz isolation ? db t a = 25 c v dd = 15 v v ss = ? 5 v v ref = 1.24 v pp ? 20 10 k figure 6. channel-to-channel isolation ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? msb lsb terminal 1 system gnd outb outa v ss refb refa agnd dgnd outc outd v dd refc refd figure 7. suggested pcb layout (top view)
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 12 post office box 655303 ? dallas, texas 75265 application information unipolar output operation the unipolar output operation is the basic mode of operation for each channel of the tlc7225, with the output voltages having the same positive polarity as v ref . the tlc7225 can be operated with a single supply (v ss = agnd) or with positive or negative supplies. the voltage at v ref must never be negative with respect to dgnd to prevent parasitic transistor turnon. connections for the unipolar output operation are shown in figure 8. the transfer values are shown in table 3. _ + dac a _ + dac b _ + dac c _ + dac d 5 refa 2 1 24 23 outa outb outc outd refb refc refd v ss agnd dgnd 4 21 20 figure 8. unipolar output circuit lsb msb dac latch contents analog output v ref 255 256 1111 1111 v ref 129 256 1000 0001 1000 0000 v ref 128 256 v ref 2 0111 1111 v ref 127 256 0000 0001 v ref 1 256 0000 0000 0 v note 3 : 1 lsb v ref 2 ? 8 v ref 1 256 table 3. unipolar code
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 13 post office box 655303 ? dallas, texas 75265 application information agnd bias for direct bipolar-output operation the tlc7225 can be used in bipolar operation without adding additional external operational amplifiers by biasing agnd to v ss as shown in figure 9. this configuration provides an excellent method for providing a direct bipolar output with no additional components. the transfer values are shown in table 4. _ + dac a agnd dgnd tlc7225 ? refa (v ref = 5 v) outa 5 22 2 7 3 v dd = 10 to 15 v 6 v ss ? digital inputs omitted for clarity. ? 5 v output range (5 v to ? 5 v) figure 9. agnd bias for direct bipolar-output operation lsb msb dac latch contents analog output v ref 127 128 1111 1111 v ref 1 128 1000 0001 1000 0000 ? v ref 128 128 v ref 0111 1111 0000 0001 v ref 127 128 0000 0000 0 v table 4. bipolar (offset binary) code v ref 1 128
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 14 post office box 655303 ? dallas, texas 75265 application information agnd bias for positive output offset the tlc7225 agnd terminal can be biased above or below the system ground terminal, dgnd, to provide an offset-zero analog-output voltage level. figure 10 shows a circuit configuration to achieve this for channel a of the tlc7225. the output voltage, v o at outa, can be expressed as: v o v bias d a v i where d a is a fractional representation of the digital input word (0 d 255/256). _ + dac a agnd dgnd tlc7225 ? v ref v o(outa) 5 22 2 7 3 v dd 6 v ss v i v bias ? digital inputs omitted for clarity. figure 10. agnd bias circuit increasing agnd above system ground reduces the output range. v dd ? v ref must be at least 4 v to ensure specified operation. since the agnd terminal is common to all four dacs, this method biases up the output voltages of all the dacs in the tlc7225. supply voltages v dd and v ss for the tlc7225 should be referenced to dgnd.
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 15 post office box 655303 ? dallas, texas 75265 application information bipolar-output operation using external amplifier each of the dacs of the tlc7225 can also be individually configured to provide bipolar output operation using an external amplifier and two resistors per channel. figure 11 shows a circuit used to implement offset binary coding (bipolar operation) with dac a of the tlc7225. in this case (see equation 1): v o 1 r2 r1 d a v ref r2 r1 v ref with r1 r2 v o 2d a 1 v ref where d a is a fractional representation of the digital word in latch a. (1) mismatch between r1 and r2 causes gain and offset errors. therefore, these resistors must match and track over temperature. the tlc7225 can be operated with a single supply or from positive and negative supplies. 15 v _ + dac a tlc7225 2 5 r2 ? r1 ? v o refa ? r1 = r2 = 10 k ? 0.1% _ + ? 15 v figure 11. bipolar-output circuit multiplying dac using ac input to the ref terminals the tlc7225 can be used as a multiplying dac when the reference signal is maintained between 2 v and v dd ? 4 v. when this configuration is used, v dd should be 14.25 v to 15.75 v. a low output-impedance buffer should be used so that the input signal is not loaded by the resistor ladder. figure 12 shows the general schematic. _ + _ + dac agnd dgnd 67 1/4 tlc7225 5, 4, 21, 20 15 v ref (a, b, c, d) op - 15 15 v r1 r2 ac reference input signal v o 15 v v dd figure 12. ac signal-input scheme
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 16 post office box 655303 ? dallas, texas 75265 application information digital word multiplication since each dac of the tlc7225 has a separate reference input, the output of one dac can be used as the reference input for another. therefore, multiplication of digital words can be performed (with the result given in analog form). for example, when the output from dac a is applied to refb then the output from dac b, v outb , can be expressed as given in equation 2: v outb = (d a ) (d b )(v refa ) (2) where d a and d b are the fractional representations of the digital words in dac latches a and b respectively. if d a = d b = d then the result is d 2 (v refa ) in this manner, the four dacs can be used on their own or in conjunction with an external summing amplifier to generate complex waveforms. figure 13 shows one such application with the output waveform, y, which is represented by equation 3: y = ? (x 4 + 2x 3 + 3x 2 + 2x + 4) v i (3) where x is the digital code that is applied to all four dac latches. _ + refa refb refc refd outa outb outc outd agnd dgnd v ss 15 v y tlc7225 ? v i ? digital inputs omitted for clarity 100 k ? 50 k ? 33 k ? 50 k ? 25 k ? 100 k ? v dd figure 13. complex-waveform generation
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 17 post office box 655303 ? dallas, texas 75265 application information microprocessor interface figures 14, 15, 16, and 17 show the hardware interface to some of the standard processors. address decode a0 a1 ldac wr db7 db0 latch en tlc7225 ? a15 a8 wr ale ad7 ad0 8085/8088 address bus address data bus ? linear circuitry omitted for clarity figure 14. tlc7225 to 8085a/8088 interface, double-buffered mode address decode a0 a1 ldac wr db7 db0 tlc7225 ? a15 a8 r/w ad7 ad0 8085/8088 address bus data bus ? linear circuitry omitted for clarity e or 2 en figure 15. tlc7225 to 6809/6502 interface, single-buffered mode
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 18 post office box 655303 ? dallas, texas 75265 application information address decode a0 a1 ldac wr db7 db0 tlc7225 ? a15 a8 mreq ad7 ad0 z-80 address bus data bus ? linear circuitry omitted for clarity wr en figure 16. tlc7225 to z-80 interface, double-buffered mode address decode a0 a1 wr db7 db0 tlc7225 ? a23 a1 as ad7 ad0 68008 address bus data bus ? linear circuitry omitted for clarity r/w en ldac dtack figure 17. tlc7225 to 68008 interface, single-buffered mode
tlc7225c, tlc7225i quadruple 8-bit digital-to-analog converters slas109b ? october 1996 ? revised february 2001 19 post office box 655303 ? dallas, texas 75265 application information linearity, offset, and gain error using single-ended supplies when an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. with a positive offset, the output voltage changes on the first code change. with a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. the output amplifier attempts to drive the output to a negative voltage. however, since the most negative supply rail is ground, the output cannot drive below ground. so with this output offset voltage, the output voltage remains at zero until the input-code value produces a sufficient output voltage to overcome the inherent offset voltage, resulting in a transfer function shown in figure 18. dac code output voltage 0 v negative offset figure 18. effect of negative offset (single supply) this offset error, not the linearity error, produces this breakpoint. the transfer function would have followed the dotted line if the output buffer could drive below ground. for a dac, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale is adjusted out or accounted for in some way. however, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. so the linearity in the unipolar mode is measured between full-scale code and the lowest code, which produces a positive output voltage. the code is calculated from the maximum specification for the zero offset error.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TLC7225CDW active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TLC7225CDWg4 active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TLC7225CDWr active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TLC7225CDWrg4 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc7225idw active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc7225idwg4 active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc7225idwr active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim tlc7225idwrg4 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-jul-2006 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated

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